Semiconductor memory device with operation limit controller
US12040043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2022 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Sep 24, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of input-output pins configured to communicate with a memory controller, a command control logic, a temperature measurement circuit and an operation limit controller. The command control logic controls an operation of the semiconductor memory device based on command signals and control signals transferred from the memory controller through control pins among the plurality of input-output pins. The temperature measurement circuit measures an operation temperature of the semiconductor memory device to generate a temperature code corresponding to the operation temperature. The operation limit controller, when it is determined based on the temperature code that the operation temperature exceeds a risk temperature, controls an internal operation of the semiconductor memory device regardless of the command signals and the control signals transferred from the memory controller to thereby decrease a power consumption of the semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.