Operating method of memory device for extending synchronization of data clock signal, and operating method of electronic device including the same
US12040046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2023 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Aug 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.