Semiconductor structure processing method and manufacturing method
US12040175B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 16, 2021 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Aug 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/308
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This application relates to a semiconductor structure processing method, including: providing a semiconductor layer including a pattern, where a trench is located amongst the pattern; cleaning the pattern using a rinse liquid, where the rinse liquid fills the trench after the cleaning; forming a flexible layer, where the flexible layer displaces the rinse liquid and fills the trench, and covers a surface of the semiconductor layer; and hardening the flexible layer and subsequently removing the flexible layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.