Fabrication method of metal-free SOI wafer
US12040221B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2022 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Feb 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26506
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.