Method for manufacturing deep trench isolation grid structure
US12040339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2021 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Sep 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a CMOS image sensor and a pixel structure thereof, and a method for manufacturing a deep trench isolation grid structure in the pixel structure. The method for manufacturing the deep trench isolation grid structure comprises: depositing a first isolation layer and a second isolation layer sequentially on the side walls and bottom surface of each deep trench; and depositing a third isolation layer that fills each deep trench on the upper surface of the second isolation layer, so that the first isolation layer, the second isolation layer and the third isolation layer in the plurality of deep trenches constitute the grid. The deep trench isolation grid structure formed by the method can effectively reduce electrical crosstalk between adjacent grid lines, thereby improving the device performance of the CMOS image sensor which is built upon the deep trench isolation grid structure and the pixel structure thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.