Diode package structure and manufacturing method thereof
US12040434B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2021 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | May 5, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A diode package structure includes a substrate, at least one diode chip and an opaque encapsulating layer. The substrate has an electrically conductive layer. At least one diode chip is mounted on the substrate and electrically connected to the electrically conductive layer. The opaque encapsulating layer has a cap portion and a sidewall portion, wherein the sidewall portion is connected to and surrounds the substrate to jointly form a concave structure, the cap portion is connected between a sidewall of the diode chip and the sidewall portion, wherein a first contact vertex of the cap portion and the sidewall of the diode chip is higher than a second contact vertex of the cap portion and the sidewall portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.