Methods and systems for controlling frequency variation for a PLL reference clock
US12040804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2022 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Apr 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This application is directed to frequency controlling in an electronic device (e.g., a retimer of a data link). The electronic device includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal with reference to the input signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller determines whether the second reference signal is in a temporal range in which the second reference signal reaches a peak frequency and controls the selector to select the second reference signal as the input signal in accordance with a determination that the second reference signal is in the temporal range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.