Resistor network with adaptive resistance for digital-to-analog converter (DAC)
US12040817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2022 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Oct 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/76
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for adaptively adjusting a resistance of a resistor network in a digital-to-analog converter (DAC), such as a current-steering DAC for a transmit chain. An example DAC generally includes a plurality of DAC cells. One or more of the DAC cells generally includes a current source and a resistor network. The resistor network includes a plurality of resistive elements, has an adjustable resistance, and is coupled between a power supply rail and the current source. In this manner, the DAC may support a wide range of full-scale currents, while maintaining a higher degeneration voltage and reduced noise and mismatch for a given headroom. For certain aspects, the one or more of the DAC cells further include a plurality of switches (e.g., implemented with PFETs) coupled to one or more of the resistive elements and configured to adjust the resistance of the resistor network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.