Memory system
US12041719B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 2021 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Feb 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/2009
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a substrate having a first and second surface, a memory controller, a nonvolatile memory, a first and second part, first and first, second, third, and fourth electrodes. The substrate includes a core portion, first and second pads on the first surface, and third and fourth pads on the second surface. The first electrodes couples the first pads and the memory controller. The second electrodes couples the second pads and the nonvolatile memory. The third electrodes couples the third pads and the first part. The fourth electrodes couples the fourth pads and the second part. The first and third pads are arranged at positions symmetrical to each other with respect to the core portion. The second and fourth pads are arranged at positions symmetrical to each other with respect to the core portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.