Chip testing method and apparatus, and electronic equipment
US12044724B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2022 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Dec 15, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2896
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A chip testing method and apparatus, and an electronic equipment are provided. The method includes: determining, according to pad distribution information of a target chip, positions of set state pads and positions of non-set state pads in the target chip, the set state pads being pads with set states, and the set states including a first state or a second state; determining a plurality of pad state setting schemes according to the positions of the set state pads and the positions of the non-set state pads, the pad state setting schemes including setting each of the non-set state pads to the first state or the second state; and determining a test voltage setting scheme satisfying a preset condition according to information of differential voltage pad pairs in each of the pad state setting schemes, the differential voltage pad pair comprising two adjacent pads in different states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.