Device, system, and method to concurrently store multiple PMON counts in a single register
US12044730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2020 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Nov 12, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/86
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.