Flip-flops and scan chain circuits including the same
US12044733B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2023 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Apr 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.