Error rate analysis method, system and apparatus for MLC chip
US12045120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2021 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Dec 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and device for analyzing an error rate of an MLC chip. The method includes selecting data blocks from the MLC chip, and performing erasing-writing operations to the data blocks; after the erasing-writing operations are completed, reading each of groups of the dual-bits corresponding to each of the first pages and the second pages of the data blocks, and determining the bit state of the each of groups of the dual-bits; counting up the first total quantity of all of the dual-bits corresponding to the target page in the target bit state representing that the data writing is erroneous, to obtain a first error rate of the target page in the target bit state; and counting up a second total quantity of all of the dual-bits corresponding to the data blocks in the target bit state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.