Preventing a processor from re-executing instructions
US12045175B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2021 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | May 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a processing unit, a memory configured to store at least one first group of instructions and one second group of instructions for execution by the processing unit, the processing unit being configured to sequentially extract from the memory instructions of the first group and instructions of the second group for their execution. The system also includes a controller including a first auxiliary memory configured to store a protection criterion, a comparator configured to compare the storage address of each extracted instruction with the protection criterion, and a control circuit configured to, in response to the storage address meeting the protection criterion, trigger a protection mechanism including at least one prohibition for the processing unit to execute again at least one portion of the instructions of the first group, during the execution of the instructions of the second group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.