Method for implementing an integrated circuit comprising a random-access memory-in-logic

US12045553B2 · kind B2 · utility

Assignee

• XENERGIC AB · SE

Inventors

• Hemanth Prabhu · Lund, SE
• Babak Mohammadi · Lund, SE

Key dates

• Filing date: Mar 13, 2020
• Grant date: Jul 23, 2024
• Expiry date: Jul 25, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A computer-implemented method for implementing integrated circuit with at least one RAM includes: defining memory portions of the RAM and obtaining memory portions; for each memory portion, generating a memory cell array block corresponding to the sizes of the memory portions, instances of the memory cell array blocks are inferred into a description of the integrated circuit in a hardware description language; for each block, generating timing and physical models; synthesizing description of circuit in the language, including peripheral logic for the blocks, to schematic representation of circuit elements; placing circuit elements, including blocks and peripheral logic, on circuit and routing wires between circuit elements taking into account the timing and physical models of blocks. An integrated circuit has memory portions of RAM, each having memory cell array block without, or partly without, peripheral logic; logic for each block implemented as standard cells, blocks and the logic distributed over circuit.