Input channel processing for triggered-instruction processing element
US12045622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2022 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Sep 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more triggered-instruction processing elements are provided, a given triggered-instruction processing element comprising execution circuitry to execute processing operations in response to instructions according to a triggered instruction architecture. Input channel processing circuitry receives a given tagged data item (comprising a data value and a tag value) for a given input channel, and in response controls enqueuing of the data value of the given tagged data item to a selected buffer structure selected from among at least two buffer structures mapped onto register storage accessible to one or more of the triggered-instruction processing elements in response to a computation instruction for controlling performance of a computation operation. The selected buffer structure is selected based at least on the tag value, so data values of tagged data items specifying different tag values for the given input channel are allocatable to different buffer structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.