Vertical memory device with metal and spacer support structure
US12046565B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2021 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Oct 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical memory device includes a cell stacked structure on a substrate, a support structure and cell contact plugs. The cell stacked structure includes gate patterns spaced apart from each other in a vertical direction and insulation layers between the gate patterns. The gate patterns extend in a first direction, and edges of the gate patterns along the first direction include step portions having step shape. The support structure passes through the cell stacked structure and the step portion of one of the gate patterns, and includes a spacer layer having cup shape, first metal patterns having ring shape, and a second metal pattern filling an inner space of the spacer layer. The cell contact plugs are on the step portions. The first metal patterns are at the same vertical levels of the gate patterns. Sidewalls of the first metal patterns are adjacent to sidewalls of the gate patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.