Time delay integration structure for complementary metal-oxide semiconductor imaging sensor
US12046624B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Nov 21, 2018 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Sep 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/807
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system is provided for time delay integration in complementary metal oxide semiconductor imaging sensors, the system comprising: a two dimensional parallel charge transfer structure comprising at least one column of CMOS Image sensor pinned photodiodes; each the diode in the column being connected to the next the diode by a two phase transfer gate, each the transfer gate having a barrier and a well configured such that a flow of charge in the column is unidirectional.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.