Integrated circuit including gate-all-around transistor
US12046653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2021 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Oct 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/43
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.