Circuit arrangement for a gate drive with a feedback resistor
US12047056B2 · kind B2 · utility
0Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2021 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Jun 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement is provided where the arrangement of a feedback resistor between a first branch and a second branch enables that a voltage is provided at an output terminal in an efficient way, this means with a high settling speed and a low current consumption. The feedback resistor is arranged between a reference node and the output terminal, where the reference node is connected to a current mirror. The circuit arrangement can be employed as a gate driver. Furthermore, a driver block and a method of driving a circuit arrangement are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.