Semiconductor device including delay compensation circuit
US12047082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2022 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Nov 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.