Semiconductor memory device
US12048143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2021 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Jun 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.