Hall integrated circuit and corresponding method of manufacturing of a hall integrated circuit using wafer stacking

US12048166B2 · kind B2 · utility

Assignee

• LFOUNDRY S.R.L. · IT

Inventors

• Carsten Schmidt · Jena, DE
• Mario Blasini · Avezzano, IT
• Gerhard Spitzlsperger · Avezzano, IT
• Alessandro Montagna · Avezzano, IT

Key dates

• Filing date: Nov 21, 2019
• Grant date: Jul 23, 2024
• Expiry date: Mar 6, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N59/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A Hall integrated circuit including a vertical Hall element, having a first wafer and a second wafer, the second wafer including a CMOS substrate integrating a CMOS processing circuit coupled to the vertical Hall element and a stack of dielectric layers, and the first wafer including a Hall-sensor layer having a first surface and a second surface, the first and second wafers being bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer. The vertical Hall element has: at least a first Hall terminal; at least a second Hall terminal; a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer; and a first and a second conductive structures electrically connected to respective contact pads embedded in the stack of the second wafer.