Interconnection structure of an integrated circuit
US12048257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2023 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Apr 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.