System halt support for synchronization pulses
US12050486B1 · kind B1 · utility
0Cited by
8References
21Claims
0Family size
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Key dates
| Filing date | Jun 6, 2022 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Sep 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.