High-density memory cells and layouts thereof
US12051457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2022 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | May 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.