Patent · US Active

Semiconductor device and fabrication method thereof

US12051737B2 · kind B2 · utility

1Cited by
0References
20Claims
0Family size

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Key dates

Filing dateAug 27, 2021
Grant dateJul 30, 2024
Priority date
Expiry dateJul 19, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D62/822
  • WIPO fieldMicro-structural and nano-technology
  • WIPO sectorChemistry

Abstract

Semiconductor device and fabrication method are provided by providing initial fins discretely arranged on a substrate; forming an isolation structure on the substrate; forming a connecting layer on sidewalls of the initial fins and between adjacent initial fins; forming a dummy gate structure across the initial fins and the connecting layer on the substrate, covering sidewalls of the connecting layer and a portion of a top surface of the initial fins; forming grooves in the initial fins on both sides of the dummy gate structure, and forming source and drain doped layers in the grooves; forming a dielectric layer on the substrate, covering sidewalls of the dummy gate structure and the source and drain doped layers, that a top surface of the dielectric layer is flush with a top surface of the dummy gate structure; and removing the dummy gate structure to form a gate structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.