Transistor and method for manufacturing the same
US12051755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2021 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | May 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/512
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.