Flash memory device and method thereof
US12051756B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 13, 2022 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Jul 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.