Fast locking dual loop clock and data recovery circuits
US12052023B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2023 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Jan 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0992
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.