SAR ADC and electronic device
US12052028B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 2022 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Nov 17, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A SAR ADC and an electronic device are disclosed. The SAR ADC includes a read clock generation circuit, configured to connect to a first output terminal and a second output terminal of a dynamic comparator, and generate a read clock signal for reading a first or a second comparison result based on the first and the second comparison result received from the dynamic comparator. The invention reads the comparison result using the read clock signal generated by grabbing the output of the comparator, and can improve the overall analog-to-digital conversion speed of the SAR ADC. Further, the present invention can detect the occurrence of metastable state of the comparator by judging that the output of the comparator has no pulse, and read the comparison result based on the backup clock generated by the operating clock of the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.