Semiconductor memory device and method of fabricating the same
US12052852B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2021 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Nov 22, 2042 |
Classification
- Technology area (CPC —)General
Abstract
A semiconductor memory device includes a static random access memory (SRAM) cell that is provided on a substrate and includes a pass-gate transistor, a pull-down transistor, and a pull-up transistor. Each of the pass-gate transistor, the pull-down transistor, and the pull-up transistor includes an active fin protruding above a device isolation layer, a gate electrode on the active fin, and a gate insulating layer between the active fin and the gate electrode. The gate insulating layer of the pull-down transistor includes a first dipole element. The highest concentration of the first dipole element of the gate insulating layer of the pull-down transistor is higher than the highest concentration of the first dipole element of the gate insulating layer of the pass-gate transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.