Array substrate and liquid crystal display panel
US12055830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2021 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Dec 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/40
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate and a liquid crystal display panel are disclosed. In the array substrate, a shared common electrode and a gate scanning line are disposed on a same layer, and a drain electrode of a third thin film transistor is electrically connected to the shared common electrode by a conductive film layer. Therefore, the shared common electrode only exists in a non-display area between a primary pixel electrode and a sub pixel electrode and does not need to pass the primary pixel electrode and the sub pixel electrode, thereby improving an aperture ratio of pixel electrodes and transmittances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.