System, device, and method for accessing memory based on multi-protocol
US12056066B2 · kind B2 · utility
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5References
18Claims
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Key dates
| Filing date | Sep 3, 2021 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Oct 17, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device configured to communicate through a bus may include a first interface circuit configured to, based on a first protocol, provide first access to a first memory through the bus and a second interface circuit configured to, based on a second protocol, provide a non-coherent input/output (I/O) interface through the bus. The second interface circuit may be configured to access the first memory in response to a message received through the bus based on the second protocol to provide second access to the first memory through the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.