Low latency memory notification
US12056072B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2021 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Dec 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques to reduce the latency of data transfer notifications in a computing system are disclosed. The techniques can include receiving, at a memory, a first access request of a set of access requests associated with a data transfer. The first access request has a token and an access count indicating the number of access requests in the set of access requests. A counter is initiated to count the number of received access requests having the token. When additional access requests belonging to the set of access requests are received, the counter is incremented for each of the additional access requests being received. A notification is transmitted to an integrated circuit component in response to receiving the last access request of the set of access requests having the token to notify the integrated circuit component that the memory is ready for access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.