Memory device having reduced power noise in refresh operation and operating method thereof
US12056371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Jan 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides methods, apparatuses, and systems having reduced power noise in a refresh operation. In some embodiments, an operating method includes: performing, in response to receiving a first refresh command, a first normal refresh, at a first refresh timing, in which first N word lines of a plurality of word lines are simultaneously refreshed, and a first target refresh, at a second refresh timing, on at least one first victim word line that is adjacent to a maximum activated word line that is most frequently activated from among the plurality of word lines; and performing, in response to receiving a second refresh command, a second normal refresh, at a third refresh timing, in which second N word lines are simultaneously refreshed, and a second target refresh, at a fourth refresh timing, on at least one second victim word line that is adjacent to the maximum activated word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.