Dynamic memory coherency biasing techniques
US12056374B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Feb 3, 2021 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Jul 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic bias coherency configuration engine can include control logic, a host threshold register, and device threshold register and a plurality of memory region monitoring units. The memory region monitoring units can include a starting page number register, an ending page number register, a host access register and a device access register. The memory region monitoring units can be utilized by dynamic bias coherency configuration engine to configure corresponding portions of a memory space in a device bias mode or a host bias mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.