Post-routing path delay prediction method for digital integrated circuit
US12056428B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2023 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Jan 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.