Method and apparatus for providing non-compute unit power control in integrated circuits
US12056535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2020 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Jul 12, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on an integrated circuit (IC), and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.