Reducing parasitic interactions in a qubit grid for surface code error correction
US12056575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2023 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Aug 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/177
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for performing a surface code error detection cycle. In one aspect, a method includes initializing and applying Hadamard gates to multiple measurement qubits; performing entangling operations on a first set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a first direction; performing entangling operations on a second set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a second or third direction, the second and third direction being perpendicular to the first direction, the second direction being opposite to the third direction; performing entangling operations on a third set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a fourth direction, the fourth direction being opposite to the first direction; applying Hadamard gates to the measurement qubits; and measuring the measurement qubits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.