Display device including level shifter generating gate clock signals synchronized with rising edge and falling edge of clock signal
US12057076B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Dec 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display device may include a timing controller which generates on-clock and off-clock signals, a level shifter which sequentially generates gate clock signals each having a rising edge and a falling edge respectively synchronized with a rising edge of the on-clock signal and a falling edge of the off-clock signal, the gate clock signals having a voltage corresponding to a gate driving voltage, a gate driver generating gate signals based on the gate clock signals, an over-current detector detecting an over-current by sensing a current of each of the gate clock signals at a time point when the falling edge of the on-clock signal is generated in an on-current detection mode, and generates a shutdown signal in response to the detected over-current, and a voltage generator providing the gate driving voltage to the level shifter and stops providing the gate driving voltage in response to the generated shutdown signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.