Shift register circuit
US12057181B2 · kind B2 · utility
0Cited by
7References
6Claims
0Family size
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Key dates
| Filing date | Dec 5, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Dec 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register circuit, including: a plurality of clock signal lines each supplying a clock pulse respectively; a plurality of cascade-connected register circuits including a top register circuit, and main register circuits providing between the top register circuit and the bottom register circuit; and a forward scan signal line supplying a forward scan signal to the plurality of cascade-connected register circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.