Clock synchronizing method of a multiple clock domain memory device
US12057193B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2023 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Feb 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.