Memory device, operating method of the memory device and memory system comprising the memory device
US12057194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2023 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | May 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.