Wafer-level etching methods for planar photonics circuits and devices

US12057332B2 · kind B2 · utility

Assignee

• Ayar Labs, Inc. · US

Inventors

• Chen Sun · Berkeley, US
• Roy Meade · Boise, US
• Mark Wade · Berkeley, US
• Alexandra Wright · San Francisco, US
• Vladimir Stojanovic · Lexington, US

Key dates

• Filing date: Jul 10, 2017
• Grant date: Aug 6, 2024
• Expiry date: May 13, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G02B2006/12061
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A photoresist material is deposited, patterned, and developed on a backside of a wafer to expose specific regions on the backside of chips for etching. These specific regions are etched to form etched regions through the backside of the chips to a specified depth within the chips. The specified depth may correspond to an etch stop material. Etching of the backside of the wafer can also be done along the chip kerf regions to reduce stress during singulation/dicing of individual chips from the wafer. Etching of the backside of the chips can be done with the chips still part of the intact wafer. Or, the wafer having the pattered and developed photoresist on its backside can be singulated/diced before etching through the backside of the individual chips. The etched region(s) formed through the backside of a chip can be used for attachment of optical component(s) to the chip.