EM and RF mitigation silicon structures in stacked die microprocessors for die to platform and die-die RF noise suppression
US12057433B2 · kind B2 · utility
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26Claims
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Key dates
| Filing date | Jun 23, 2020 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Dec 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2001/0085
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein include electronic packages and their components. In an embodiment, an electronic package comprises a package substrate and a base die over the package substrate. In an embodiment, the electronic package further comprises a plurality of chiplets over the base die. In an embodiment, the base die comprises a substrate, a first metal layer and a second metal layer between the substrate and the plurality of chiplets, and a third metal layer and a fourth metal layer between the package substrate and the substrate. In an embodiment, a filter is integrated into one or more layers of the base die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.