Minimization of silicon germanium facets in planar metal oxide semiconductor structures
US12057504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Jul 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/013
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.