Pulse-width modulation circuit
US12057843B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2023 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Apr 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pulse-width modulation (PWM) circuit includes a partition circuit coupled to receive a PWM value representing a duty cycle of a PWM signal to be generated, and configured to accordingly generate a most-significant-bits (MSB) value representing higher-order bits of the PWM value and a least-significant-bits (LSB) value representing lower-order bits of the PWM value; a PWM generator coupled to receive the MSB value or a derivative thereof, and configured to accordingly generate a primary signal with a duty cycle corresponding to the MSB value; a delay circuit that generates a delay signal representing the primary signal with delay time determined according to the LSB value or a derivative thereof; and a combine circuit that generates the PWM signal according to the primary signal and the delay signal, by performing a logical operation on the primary signal and the delay signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.