Test substrate and manufacturing method therefor, test method, and display substrate
US12058924B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 23, 2019 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Sep 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1213
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A test substrate has at least one test region and includes a base substrate, a plurality of thin film transistors disposed on the base substrate, at least one test hole located in the test region, and at least one test pin. At least one of the thin film transistors is a target thin film transistor to be tested, each target thin film transistor is located in one test region. Each test hole exposes a source region, a drain region or a gate of a corresponding target thin film transistor at a bottom thereof. Each test pin is located in one test hole. One end of the test pin passes through the test hole to be coupled to the source region, the drain region or the gate of the corresponding target thin film transistor, and another end of the test pin is exposed at a surface of the test substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.