SOC PMUT suitable for high-density system integration, array chip, and manufacturing method thereof
US12060264B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2022 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Jan 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N30/8554
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an SOC PMUT suitable for high-density system integration, an array chip and a manufacturing method thereof. With the SOC PMUT suitable for high-density system integration, vertical stacking and monolithic integration of a SOC PMUT array with CMOS auxiliary circuits is realized by means of direct bonding of active wafers and a vertical multi-channel metal wiring structure; in addition, the extension to the package layer is implemented by means of TSVs, without any bonding mini-pad on the periphery of the array for communication with the CMOS. Thus, the bottleneck of metal interconnections in conventional ultrasonic transducers is overcome, the chip area occupied by metal interconnections in ultrasonic transducers is greatly reduced, the metal wiring length is reduced, thus the resulting adverse effects of an electrical parasitic effect on the performance of the ultrasonic transducer array are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.